The present invention relates to semiconductor processing. More specifically, the present invention relates to a method and apparatus for forming a halogen-doped silicon oxide film having low compressive stress. The film of the present invention is particularly useful as an intermetal dielectric (IMD) layer in a multiple metal layer structure, but may also be employed as a premetal dielectric layer, passivation layer, or the like.
One of the primary steps in the fabrication of modern semiconductor devices is the formation of a film, such as a silicon oxide, on a semiconductor substrate. Silicon oxide is widely used as an insulating layer, such as an IMD layer, in the manufacture of semiconductor devices. A silicon oxide film can be deposited by thermal chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD) processes. In a conventional thermal CVD process, reactive gases are supplied to the substrate surface where heat-induced chemical reactions (homogeneous or heterogeneous) take place to produce a desired film. In a conventional plasma process, a controlled plasma is formed to decompose and/or energize reactive species to produce the desired film. In general, reaction rates in thermal and plasma processes may be controlled by controlling one or more of the following: temperature, pressure, and reactant gas flow rate.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two-year/half-size rule (often called "Moore's Law") which means that the number of devices which will fit on a chip doubles every two years. Wafer fabrication plants are routinely producing devices with 0.5 .mu.m and even 0.35 .mu.m size features. Fabrication plants soon will be producing devices having even smaller geometries. As device sizes become smaller and integration density increases, issues which were not previously considered important by the industry are becoming of concern.
In modern devices utilizing multilevel metal technology in which three, four, or more layers of metal are formed on the semiconductor substrate, the properties of insulating films used as IMD layers are increasingly important. In particular, insulating films for IMD applications need to have, for example, low dielectric constants, good gap fill capability, and low compressive intrinsic stress. Low dielectric constant films used as IMD layers are required in order to reduce the RC time delay of the interconnect metallization, to prevent cross-talk between the different levels of metallization, and to reduce device power consumption. In addition to having low dielectric constants, films used as IMD layers need good gap fill capability. That is, the layers should exhibit good step coverage and planarization properties to produce void-free layers that completely fill steps and openings in the underlying layers. As device sizes become smaller and integration density increases, it becomes critical to control the intrinsic stress level of films used as IMD layers. Such films need to have an overall low compressive stress, because intrinsic stress levels above or below certain levels may lead to wafer bowing, film cracking, void formation in the film, or other problems. Specifically, high tensile stress in the film causes the substrate to bend in a concave manner, while high compressive stress in the film causes the substrate to bend in a convex manner. It is optimal that IMD layers have a low compressive stress, avoiding concave or convex bending of the substrate, in order to avoid hillocking of metal during subsequent processing steps.
Conventional approaches to forming films suitable for use as IMD layers in some applications have proven limited in applications with more stringent requirements. For example, halogen-doped silicon glass films, such as fluorinated silicon glass (FSG) films, deposited by a plasma-enhanced process generally are compressively stressed, but step coverage or gap-filling capability for complex or smaller device geometries may be inhibited by the directionality of the plasma process. As another example, thermally-deposited ozone (O.sub.3)/tetraethylorthosilicate (TEOS) films, such as borosilicate glass (BSG) films, phosphosilicate glass (PSG) films, and borophosphosilicate glass (BPSG) films, sometimes used as IMD layers have high tensile stresses (greater than about 1-2.times.10.sup.9 dynes/cm.sup.2) that may result in concave bending of the substrate.
In another conventional approach, an undoped silicon glass (USG) film formed from a thermal O.sub.3 /TEOS CVD process has a low dielectric constant suitable for IMD applications. Such films, referred to as O.sub.3 /TEOS USG films, also exhibit good gap-filling capability for devices having about 0.25 .mu.m spacing or less and greater than about 2.5:1 aspect ratios. However, O.sub.3 /TEOS USG films have high tensile intrinsic stress (on the order of 3.times.10.sup.9 dynes/cm.sup.2). In order to cover deep gaps adequately, such O.sub.3 /TEOS USG films need to be thick, e.g., about 0.6 .mu.m thick, in some applications. As a result, the thick O.sub.3 /TEOS USG film has high cumulative tensile stresses which have been counteracted by forming a compressively stressed capping layer using a PECVD process over the O.sub.3 /TEOS USG film. To counteract the high tensile stress of the thick O.sub.3 /TEOS USG layer, a relatively thick (e.g., greater about 1.5 .mu.m thick) PECVD capping layer having a high compressive stress is required. Therefore, the composite insulating layer (made of the thick O.sub.3 /TEOS USG layer and the thick PECVD capping layer) has a large overall thickness (e.g., about 2.1 .mu.m) for managing the overall stress of the composite insulating layer in IMD applications requiring filling of deep gaps.
Although it can provide film properties suitable for advanced IMD applications and manages the overall film stress, the use of a thick composite insulating layer made of an O.sub.3 /TEOS USG layer and PECVD capping layer has drawbacks such as resulting in both processing inefficiency and device performance issues. Specifically, deposition of such a thick insulating layer increases the overall time required for substrate processing and decreases wafer throughput. With modern devices having multiple IMD layers, the processing inefficiencies become exaggerated. Moreover, processing steps, such as forming deep vias through the thick composite insulating layer and adequately filling these deep vias with a desired filling material, which are performed after the deposition of the composite insulating layer further add to the overall substrate processing time. Filling the deep vias formed in the thick composite insulating layer may result in voids formed in the filling material which may affect device performance. Accordingly, it is desirable that the overall thickness of the insulating film having film properties suitable for use as an IMD layer in modern devices be minimized in order to increase wafer throughput by reducing the substrate processing time and to avoid problems associated with filling deep vias in the composite insulating layer.
The issues arising from the use of a thick composite insulating layer of an O.sub.3 /TEOS USG layer and PECVD capping layer as an IMD layer have not been satisfactorily resolved. For example, one approach used to reduce the overall thickness of the composite insulating layer is to perform an etch or a chemical mechanical polish (CMP) of the PECVD capping layer formed on the thick O.sub.3 /TEOS USG layer. However, a thick PECVD capping layer having high compressive stress needs to remain on the thick O.sub.3 /TEOS USG layer in order to manage the overall film stress and avoid film cracking. Another approach to reducing the overall thickness of the composite insulating layer is to use a thinner initial O.sub.3 /TEOS USG layer. However, use of a thinner O.sub.3 /TEOS USG layer can result in voids in the PECVD capping layer within wider gaps. Such voids are undesirable because they can lead to device problems.
In view of the above, an alternative approach is desired to produce a thin, low dielectric constant film, having good gap fill capability and low compressive intrinsic stress, that is suitable for complex or small device geometries in IMD applications and other applications.